US 11,901,913 B1
Error correction coding apparatus and error correction decoding apparatus
Hideo Yoshida, Tokyo (JP); Tsuyoshi Yoshida, Tokyo (JP); Yoshiaki Konishi, Tokyo (JP); and Kenji Ishii, Tokyo (JP)
Assigned to MITSUBISHI ELECTRIC CORPORATION, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Aug. 31, 2022, as Appl. No. 17/899,719.
Application 17/899,719 is a continuation of application No. PCT/JP2021/004798, filed on Feb. 9, 2021.
Claims priority of application No. PCT/JP2020/015223 (WO), filed on Apr. 2, 2020.
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1131 (2013.01) [H03M 13/611 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An error correction decoding apparatus to perform error correction decoding, the apparatus comprising:
a parity bit syndrome circuit to perform a syndrome operation of parity bits included in a multilevel modulation symbol, the multilevel modulation symbol having being error correction coded by the error correction coding apparatus using, as an error correction code sequence, a frame of m bits×n parallel symbols defining a multilevel symbol and input in m-bit parallel where m and n are positive integers, the parity bits being error correction coded, the error correction coding apparatus replacing known bits assigned to a bit sequence specified in the error correction code sequence, with the parity bits, the multilevel modulation symbol being input in m-bit parallel;
an information bit syndrome circuit to perform a syndrome operation of information bits and the known bits included in the multilevel modulation symbol, the known bits replacing the parity bits included in the multilevel modulation symbol; and
an error correction decoding circuit to perform error correction decoding, using syndrome data calculated by the parity bit syndrome circuit and the information bit syndrome circuit.