| CPC H03M 13/1128 (2013.01) [H03M 13/1111 (2013.01); H03M 13/1575 (2013.01)] | 12 Claims |
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1. A memory controller, for use in a data storage device, wherein a low-density parity check (LDPC) process performed by the memory controller comprises an initial phase, a decoding phase, and an output phase, the memory controller comprising:
a variable-node circuit; and
a check-node circuit,
wherein during the initial phase, the variable-node circuit performs the following steps:
obtaining a channel value, that is read from a flash memory, from a channel-value memory;
transmitting the channel value to the check-node circuit to calculate a syndrome; and
in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory to 0, and entering the decoding phase;
wherein in the decoding phase, during each LDPC decoding iterative operation, the variable-node circuit performs the following steps:
calculating a syndrome weight according to the syndrome;
obtaining one or more first codeword bits in the previous codeword with the value of the register being 1 from the variable-node memory, and regarding other second codeword bits in the previous codeword as 0;
performing a bit-flipping algorithm according to the syndrome weight to flip one or more codeword bits in the first codeword bits and the second codeword bits in the previous codeword to generate an updated codeword;
subtracting the previous codeword from the updated codeword to generate a codeword difference; and
transmitting the codeword difference to the check-node circuit to update the syndrome.
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