US 11,901,906 B1
Hybrid fractional-N sampling phase locked loop (PLL) with accurate digital-to-time converter (DTC) calibration
Abhishek Bhat, Allentown, PA (US); Romesh Kumar Nandwana, Chapel Hill, NC (US); Pavan Kumar Hanumolu, Champaign, IL (US); and Kadaba Lakshmikumar, Hillsborough, NJ (US)
Assigned to CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Aug. 15, 2022, as Appl. No. 17/887,709.
Int. Cl. H03L 7/099 (2006.01); G06N 3/063 (2023.01); H03B 7/08 (2006.01); H04B 1/16 (2006.01); G06G 7/60 (2006.01); G04F 10/00 (2006.01); H03L 7/091 (2006.01)
CPC H03L 7/099 (2013.01) [G04F 10/005 (2013.01); G06G 7/60 (2013.01); G06N 3/063 (2013.01); H03B 7/08 (2013.01); H03L 7/091 (2013.01); H04B 1/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator;
supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter;
supplying an output of the digital-to-time converter to an input of the sampling phase detector; and
supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator,
wherein a circuit path between the comparator and the integral control input of the voltage-controlled oscillator is devoid of a transconductance amplifier.