US 11,901,902 B2
Integrated circuit including flip-flop and computing system for designing the integrated circuit
Seungman Lim, Siheung-si (KR); Minsu Kim, Hwaseong-si (KR); and Ahreum Kim, Daegu (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 16, 2022, as Appl. No. 17/696,086.
Claims priority of application No. 10-2021-0066827 (KR), filed on May 25, 2021; and application No. 10-2022-0028935 (KR), filed on Mar. 7, 2022.
Prior Publication US 2022/0385277 A1, Dec. 1, 2022
Int. Cl. H03K 3/02 (2006.01); H03K 3/037 (2006.01); H03K 17/687 (2006.01); H03K 3/3562 (2006.01)
CPC H03K 3/0372 (2013.01) [H03K 3/3562 (2013.01); H03K 17/6872 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first flip-flop configured to operate in synchronization with a clock signal, wherein the first flip-flop includes,
a multiplexer configured to receive a scan enabled signal, a scan input signal, a data input signal, and a reset input signal, the multiplexer configured to output an inverted signal of the scan input signal to a first node based on the scan enable signal, the multiplexer configured to output an inverted signal of the data input signal or a signal having a first level to the first node based on the reset input signal, the multiplexer configured to selectively output the inverted signal of the scan input signal, the inverted signal of the data input signal, or the signal having the first level to the first node based on the reset input signal and the scan enable signal,
a master latch configured to latch the output signal through the first node, and to output the latched signal, and
a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.