CPC H03K 21/403 (2013.01) [G06F 7/607 (2013.01); H03K 23/005 (2013.01)] | 13 Claims |
1. A monotonic counter memory system, comprising:
a counter circuit, configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer; and
a memory circuit, comprising a plurality of memory cells and configured to store the count value, wherein the stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2n−1 times.
|