US 11,901,890 B2
Multi-termination scheme interface
Lu Wang, Framingham, MA (US)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Jun. 11, 2021, as Appl. No. 17/345,984.
Application 17/345,984 is a continuation of application No. 15/789,420, filed on Oct. 20, 2017, granted, now 11,063,591.
Prior Publication US 2021/0305983 A1, Sep. 30, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/00 (2006.01); H03K 19/20 (2006.01)
CPC H03K 19/0005 (2013.01) [H03K 19/20 (2013.01)] 32 Claims
OG exemplary drawing
 
1. A method comprising:
programming a plurality of control signals including a first control signal and a second control signal that specify a target resistance and a target voltage in a circuit;
generating a plurality of gate signals based on the first control signal and the second control signal;
sending the plurality of gate signals to a plurality of transistors, each respective transistor of the plurality of transistors coupled with a respective resistor of a plurality of resistors and at least one of a voltage source and a ground to allow, when a respective gate signal enables the respective transistor, current to flow through the respective transistor, the respective resistor, and the at least one of the voltage source and the ground, wherein at least two transistors of the plurality of transistors are in parallel branches; and
providing, as an output, a signal with the target voltage and target resistance.