US 11,901,727 B2
Apparatuses and method for over-voltage event protection
James Davis, Boise, ID (US); and Michael Chaine, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Nov. 12, 2021, as Appl. No. 17/525,707.
Application 17/525,707 is a division of application No. 16/223,352, filed on Dec. 18, 2018, granted, now 11,183,837.
Application 16/223,352 is a continuation of application No. 15/050,238, filed on Feb. 22, 2016, granted, now 10,193,334, issued on Jan. 29, 2019.
Application 15/050,238 is a continuation of application No. 13/795,425, filed on Mar. 12, 2013, granted, now 9,281,682, issued on Mar. 8, 2016.
Prior Publication US 2022/0069572 A1, Mar. 3, 2022
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01)
CPC H02H 9/041 (2013.01) [H01L 27/0262 (2013.01); H02H 9/046 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a bulk material doped with a first dopant type, wherein the bulk material includes a first well doped with a second dopant type, wherein the first well includes a first region, a second region, and a second well doped with the second dopant type, wherein the second well includes a third region doped with the first dopant type, wherein the third region, the second well, the first well, and the second region together form a thyristor, wherein the first region and the first well are coupled to a reference node, wherein the third region is coupled to a pad configured to provide an input signal; and
a gate formed on a surface of the bulk material overlapping an area between the first region and the second region, wherein the gate is coupled to a trigger voltage source configured to set the trigger voltage of the thyristor.