US 11,901,462 B2
Contaminant collection on SOI
Honglin Guo, Dallas, TX (US); Zachary K Lee, Fremont, CA (US); and Jingjing Chen, Santa Clara, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Feb. 5, 2022, as Appl. No. 17/665,497.
Prior Publication US 2023/0307557 A1, Sep. 28, 2023
Int. Cl. H01L 29/94 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/40 (2006.01); H01L 21/266 (2006.01)
CPC H01L 29/94 (2013.01) [H01L 29/66189 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 29/401 (2013.01)] 37 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a semiconductor-on-insulator (SOI) substrate having a semiconductor layer over a buried insulator layer, the semiconductor layer including white space regions that include a P-type well (PWELL) region;
an electronic device that includes an N-type well (NWELL) region formed in the semiconductor layer, a dielectric formed over the NWELL region, and a polysilicon plate over the dielectric; and
a sacrificial NWELL ring adjacent to and separated from the NWELL region by a first gap.