US 11,901,457 B2
Fin shaping and integrated circuit structures resulting therefrom
Szuya S. Liao, Portland, OR (US); Rahul Pandey, Hillsboro, OR (US); Rishabh Mehandru, Portland, OR (US); Anupama Bowonder, Portland, OR (US); and Pratik Patel, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 2, 2019, as Appl. No. 16/700,431.
Prior Publication US 2021/0167209 A1, Jun. 3, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7853 (2013.01) [H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor fin having a protruding fin portion above an isolation structure above a substrate, the protruding fin portion having substantially vertical upper sidewalls and outwardly tapered lower sidewalls, and the semiconductor fin further comprising a sub-fin portion on the substrate and within an opening in the isolation structure, the sub-fin portion in contact with the protruding portion, and the sub-fin portion having an upper horizontal surface extending laterally beyond the protruding fin portion;
a gate stack over and conformal with the protruding fin portion of the semiconductor fin;
a first source or drain region at a first side of the gate stack; and
a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.