	US 11,901,455 B2
	Method of manufacturing a FinFET by implanting a dielectric with a dopant
Su-Hao Liu, Jhongpu Township (TW); Kuo-Ju Chen, Taichung (TW); Kai-Hsuan Lee, Hsinchu (TW); I-Hsieh Wong, Hsinchu (TW); Cheng-Yu Yang, Xihu Township (TW); Liang-Yin Chen, Hsinchu (TW); Huicheng Chang, Tainan (TW); Yee-Chia Yeo, Hsinchu (TW); Syun-Ming Jang, Hsinchu (TW); and Meng-Han Chou, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/813,888.
Application 17/813,888 is a division of application No. 16/879,894, filed on May 21, 2020, granted, now 11,456,383.
Claims priority of provisional application 62/894,006, filed on Aug. 30, 2019.
Prior Publication US 2022/0359755 A1, Nov. 10, 2022
Int. Cl. H01L 21/266 (2006.01); H01L 21/3115 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01)

CPC H01L 29/7851 (2013.01) [H01L 21/266 (2013.01); H01L 21/31155 (2013.01); H01L 21/764 (2013.01); H01L 21/7682 (2013.01); H01L 21/76825 (2013.01); H01L 21/76831 (2013.01); H01L 21/76897 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 29/0847 (2013.01); H01L 29/41725 (2013.01); H01L 29/41766 (2013.01); H01L 29/41791 (2013.01); H01L 29/4991 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/28518 (2013.01); H01L 21/76224 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 2221/1063 (2013.01)]

20 Claims

1. A method comprising:

forming a gate stack over a semiconductor fin;

forming an epitaxial source/drain region in the semiconductor fin adjacent the gate stack;

depositing a first dielectric layer over the gate stack and over the epitaxial source/drain region;

forming an opening in the first dielectric layer to expose the epitaxial source/drain region;

depositing a sacrificial material within the opening;

depositing a conductive material over the sacrificial material within the opening;

removing the sacrificial material to form a recess; and

implanting the first dielectric layer with a dopant, wherein after implanting the first dielectric layer the recess is covered by the first dielectric layer.

9. A method comprising:

forming a fin protruding from a semiconductor substrate;

forming a gate structure over a channel region of the fin;

forming an epitaxial source/drain region in the fin adjacent the channel region;

forming a first inter-layer dielectric (ILD) layer over the epitaxial source/drain region;

forming a second ILD layer over the gate structure and over the first ILD;

forming a source/drain contact penetrating through the first ILD and the second ILD to physically contact the epitaxial source/drain region, wherein the source/drain contact is surrounded by a first spacer layer and a second spacer layer;

etching the first spacer layer to expose sidewalls of the second spacer layer; and

performing an implantation process on the second ILD, wherein the implantation process laterally expands a first portion of the second ILD to physically contact an exposed sidewall of the second spacer layer.

16. A method comprising:

forming an epitaxial source/drain region in a semiconductor fin;

forming an isolation region over the epitaxial source/drain region;

forming a contact on the epitaxial source/drain region, wherein an air gap separates the contact and the isolation region; and

sealing the air gap, comprising implanting the isolation region with a dopant.