US 11,901,442 B2
Method of manufacturing a semiconductor device and a semiconductor device
Ya-Wen Chiu, Tainan (TW); Yi Che Chan, Hsinchu (TW); Lun-Kuang Tan, Hsinchu (TW); Zheng-Yang Pan, Zhubei (TW); Cheng-Po Chau, Tainan (TW); Pin-Chu Liang, Changhua County (TW); Hung-Yao Chen, Hsinchu (TW); De-Wei Yu, Ping-tung (TW); and Yi-Cheng Li, Yunlin County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/875,279.
Application 17/875,279 is a division of application No. 17/109,895, filed on Dec. 2, 2020, granted, now 11,677,015.
Claims priority of provisional application 63/024,377, filed on May 13, 2020.
Prior Publication US 2022/0376091 A1, Nov. 24, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/161 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66818 (2013.01) [H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02661 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/1037 (2013.01); H01L 29/161 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor fin disposed over a semiconductor substrate and extending in a first direction, the semiconductor fin including a channel region and a bottom region on which the channel region is disposed;
a liner dielectric layer disposed on side walls of the bottom region;
an isolation insulating layer from which the channel region protrudes and in which the bottom region is embedded; and
a gate structure disposed over the channel region of the semiconductor fin and extending in a second direction crossing the first direction, wherein:
a cap semiconductor layer is disposed on the channel region,
a top of the liner dielectric layer is only partially covered by the cap semiconductor layer, and
a thickness of the cap semiconductor layer on the liner dielectric layer is greater than a thickness of the cap semiconductor layer at a 50% height of the channel region.