US 11,901,441 B2
Fin field-effect transistor and method of forming the same
Jian-Jou Lian, Tainan (TW); Tzu Ang Chiang, I-lan (TW); Ming-Hsi Yeh, Hsinchu (TW); Chun-Neng Lin, Hsinchu (TW); Po-Yuan Wang, Hsinchu (TW); and Chieh-Wei Chen, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 10, 2023, as Appl. No. 18/167,402.
Application 18/167,402 is a continuation of application No. 17/070,634, filed on Oct. 14, 2020, granted, now 11,588,041.
Prior Publication US 2023/0187543 A1, Jun. 15, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a gate trench over a semiconductor fin, the gate trench including a top portion over a bottom portion that is narrower than the top portion;
depositing a glue layer in the gate trench, the glue layer including a second sub-layer over a first sub-layer, wherein the first and the second sub-layers differ in composition, and wherein a portion of the first sub-layer completely fills the bottom portion of the gate trench; and
removing a portion of the glue layer from the top portion of the gate trench to expose the portion of the first sub-layer in the bottom portion of the gate trench.