US 11,901,422 B2
Semiconductor device having fin-type active patterns with shared contact plugs
Deok Han Bae, Hwaseong-si (KR); Hyung Jong Lee, Osan-si (KR); and Hyun Jin Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 7, 2021, as Appl. No. 17/224,269.
Application 17/224,269 is a continuation of application No. 16/406,472, filed on May 8, 2019, granted, now 10,998,411.
Application 16/406,472 is a continuation of application No. 15/844,960, filed on Dec. 18, 2017, granted, now 10,347,726, issued on Jul. 9, 2019.
Claims priority of application No. 10-2017-0042970 (KR), filed on Apr. 3, 2017.
Prior Publication US 2021/0257470 A1, Aug. 19, 2021
Int. Cl. H01L 27/08 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H10B 10/00 (2023.01); H01L 27/02 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 21/823475 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H10B 10/12 (2023.02); H01L 21/823425 (2013.01); H01L 27/0207 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a fin-type active pattern extended on the substrate in a first direction;
a gate structure extended on the substrate in a second direction different from the first direction, the gate structure intersecting the fin-type active pattern, and the gate structure including sidewall spacers on opposite sidewalls thereof;
an active area on a side of the gate structure in the fin-type active pattern and serving as a source/drain region;
an insulating layer on the substrate, the insulating layer covering the fin-type active pattern and the gate structure;
a shared contact plug penetrating through the insulating layer, the shared contact plug including:
a first lower portion and a second lower portion connected to the active area and the gate structure, respectively, the insulating layer having a first portion between the first lower portion and the second lower portion, and
an upper portion connecting upper surfaces of the first lower portion and the second lower portion; and
a silicon nitride film between the first lower portion and the second lower portion, the silicon nitride film surrounding a sidewall of the first lower portion and the second lower portion,
wherein the insulating layer includes a second portion between the silicon nitride film and a corresponding one of the sidewall spacers of the gate structure, and
wherein a bottom of the second lower portion has a flat area and is at a level higher than a bottom of the first lower portion.