US 11,901,418 B2
GaN/diamond wafers
Won Sang Lee, Chapel Hill, NC (US)
Assigned to RFHIC Corporation, Anyang-si (KR)
Filed by RFHIC Corporation, Anyang-si (KR)
Filed on Feb. 23, 2022, as Appl. No. 17/678,975.
Application 17/678,975 is a division of application No. 16/914,474, filed on Jun. 29, 2020, granted, now 11,476,335.
Claims priority of provisional application 62/971,869, filed on Feb. 7, 2020.
Prior Publication US 2022/0181450 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 29/20 (2006.01); H01L 21/02 (2006.01); H01L 29/205 (2006.01); H01L 29/267 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 23/00 (2006.01)
CPC H01L 29/2003 (2013.01) [H01L 21/0254 (2013.01); H01L 21/02378 (2013.01); H01L 21/02488 (2013.01); H01L 21/02527 (2013.01); H01L 21/76871 (2013.01); H01L 21/76897 (2013.01); H01L 24/94 (2013.01); H01L 29/1602 (2013.01); H01L 29/205 (2013.01); H01L 29/267 (2013.01); H01L 29/66462 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for processing a semiconductor wafer, comprising:
disposing and patterning a first metal layer on a semiconductor layer of a semiconductor wafer, wherein the semiconductor wafer includes a support wafer, a diamond layer, an intermediate layer and the semiconductor layer;
drilling one or more holes from the first metal layer toward the support wafer to thereby form one or more vias that extend from the first metal layer into the support wafer;
disposing a second metal layer on the first metal layer and in a portion of the one or more vias; and
removing the support wafer to expose a surface of the diamond layer.