US 11,901,404 B2
Capacitor architectures in semiconductor devices
Sudipto Naskar, Portland, OR (US); Manish Chandhok, Beaverton, OR (US); Abhishek A. Sharma, Portland, OR (US); Roman Caudillo, Portland, OR (US); Scott B. Clendenning, Portland, OR (US); and Cheyun Lin, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 18, 2022, as Appl. No. 17/578,043.
Application 17/578,043 is a division of application No. 16/828,497, filed on Mar. 24, 2020, granted, now 11,264,449.
Prior Publication US 2022/0140068 A1, May 5, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC H01L 28/87 (2013.01) [H10B 12/033 (2023.02); H10B 12/31 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, the method comprising:
forming a transistor, wherein the transistor includes a channel along a first direction;
forming a pole placed in a second direction orthogonal to the first direction;
forming a first electrode surrounding and coupled to the pole;
forming a dielectric layer surrounding the first electrode, and
forming a second electrode surrounding the dielectric layer, wherein the first electrode, the dielectric layer, and the second electrode form a capacitor unit around the pole, wherein the capacitor unit is a first capacitor unit, and the method further comprises:
forming a second capacitor unit above the first capacitor unit, wherein forming the second capacitor unit includes:
forming a first electrode of the second capacitor unit surrounding and coupled to the pole and above the first capacitor unit;
forming a dielectric layer of the second capacitor unit surrounding the first electrode of the second capacitor, and
forming a second electrode of the second capacitor unit surrounding the dielectric layer of the second capacitor.