US 11,901,400 B2
MFM capacitor and process for forming such
Nazila Haratipour, Hillsboro, OR (US); Chia-Ching Lin, Portland, OR (US); Sou-Chi Chang, Portland, OR (US); Ashish Verma Penumatcha, Hillsboro, OR (US); Owen Loh, Portland, OR (US); Mengcheng Lu, Portland, OR (US); Seung Hoon Sung, Portland, OR (US); Ian A. Young, Portland, OR (US); Uygar Avci, Portland, OR (US); and Jack T. Kavalieros, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 29, 2019, as Appl. No. 16/369,737.
Prior Publication US 2020/0312950 A1, Oct. 1, 2020
Int. Cl. H01L 49/02 (2006.01); H01G 4/012 (2006.01); H01G 4/30 (2006.01); H01L 23/522 (2006.01); H10B 51/00 (2023.01)
CPC H01L 28/56 (2013.01) [H01G 4/012 (2013.01); H01G 4/30 (2013.01); H01L 23/5226 (2013.01); H10B 51/00 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A capacitor, comprising:
a first metal layer in a trench in a dielectric layer, the first metal layer having an uppermost surface at a same level as an uppermost surface of the dielectric layer;
a seed layer on the first metal layer, the seed layer including a polar phase crystalline structure;
a ferroelectric layer on the seed layer, the ferroelectric layer along and in contact with the uppermost surface of the dielectric layer; and
a second metal layer on the ferroelectric layer, wherein the ferroelectric layer extends laterally beyond the second metal layer and laterally beyond the first metal layer, and wherein the ferroelectric layer has a bottommost surface below the uppermost surface of the first metal layer.