US 11,901,362 B2
Semiconductor device and method
Hsin-Yi Lee, Hsinchu (TW); Weng Chang, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/884,052.
Application 17/884,052 is a continuation of application No. 17/182,733, filed on Feb. 23, 2021, granted, now 11,502,081.
Claims priority of provisional application 63/137,326, filed on Jan. 14, 2021.
Prior Publication US 2022/0384440 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/0228 (2013.01); H01L 29/0665 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
first nanostructures;
a gate dielectric on the first nanostructures; and
a first gate electrode comprising:
a first layer on the gate dielectric, the first layer comprising an n-type work function metal, the first layer being disposed in an area between the first nanostructures;
a second layer on the first layer, the second layer comprising a barrier material, the barrier material being different from the n-type work function metal, the area between the first nanostructures being free of the second layer; and
a third layer on the second layer, the third layer comprising a p-type work function metal, the p-type work function metal being different from the n-type work function metal, the p-type work function metal being different from the barrier material.