US 11,901,360 B2
Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory
Lars Liebmann, Mechanicville, NY (US); Jeffrey Smith, Clifton Park, NY (US); Anton J. deVilliers, Clifton Park, NY (US); and Kandabara Tapily, Mechanicville, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Nov. 23, 2021, as Appl. No. 17/456,225.
Application 17/456,225 is a division of application No. 16/560,490, filed on Sep. 4, 2019, granted, now 11,217,583.
Claims priority of provisional application 62/727,097, filed on Sep. 5, 2018.
Prior Publication US 2022/0085012 A1, Mar. 17, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 23/535 (2006.01); H01L 29/417 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 21/3213 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 21/768 (2006.01); H03K 19/0948 (2006.01); H01L 27/02 (2006.01); H01L 29/10 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/32139 (2013.01); H01L 21/76895 (2013.01); H01L 21/8221 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/41758 (2013.01); H01L 29/42376 (2013.01); H03K 19/0948 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
forming a plurality of transistor pairs that are stacked over a substrate, wherein the plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs, wherein each of the plurality of transistor pairs comprises a n-type transistor and a p-type transistor that are stacked over one another; and
performing a sequence of vertical and lateral etch steps to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.