US 11,901,319 B2
Semiconductor package system and method
Hui-Min Huang, Taoyuan (TW); Chih-Wei Lin, Zhubei (TW); Tsai-Tsung Tsai, Taoyuan (TW); Ming-Da Cheng, Taoyuan (TW); Chung-Shi Liu, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 19, 2021, as Appl. No. 17/233,967.
Application 15/268,739 is a division of application No. 14/447,371, filed on Jul. 30, 2014, granted, now 9,449,908, issued on Sep. 20, 2016.
Application 17/233,967 is a continuation of application No. 16/716,106, filed on Dec. 16, 2019, granted, now 10,985,122.
Application 16/716,106 is a continuation of application No. 16/042,162, filed on Jul. 23, 2018, granted, now 10,510,697, issued on Dec. 17, 2019.
Application 16/042,162 is a continuation of application No. 15/268,739, filed on Sep. 19, 2016, granted, now 10,032,734, issued on Jul. 24, 2018.
Prior Publication US 2021/0242150 A1, Aug. 5, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 21/481 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/49861 (2013.01); H01L 23/49866 (2013.01); H01L 23/5389 (2013.01); H01L 24/07 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 21/568 (2013.01); H01L 23/49827 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/29386 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/94 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/18162 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first surface, wherein the first surface comprises a protective material and an encapsulating material, wherein the protective material extends a first distance from the first surface to a second surface opposite the first surface and wherein the encapsulating material extends a second distance from the first surface to a third surface opposite the first surface, the second distance being greater than the first distance, wherein a semiconductor die is in physical contact with the second surface of the protective material and wherein the semiconductor die extends a third distance from the second surface to a fourth surface facing away from the second surface, wherein the second distance is at least as large as a sum of the first distance and the third distance, wherein the protective material has a first width and the semiconductor die has a second width greater than the first width; and
forming a conductive material extending over both the protective material and the encapsulating material, the conductive material also extending through the protective material to be in electrical contact with the semiconductor die, wherein the conductive material comprises a seed layer.