| CPC H01L 23/562 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
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1. A method of fabricating a memory device, comprising:
providing a substrate, wherein the substrate comprises a first tile region and a second tile region;
forming a conductive layer over the substrate;
forming a stacked structure on the conductive layer, wherein stacked structure comprises multiple insulating layers and multiple sacrificial layers which alternate with each other;
patterning the stacked structure to form a first staircase structure in the first tile region and a second staircase structure in the second tile region;
patterning the conductive layer to form a first slit trench along a first direction in the conductive layer and between the first tile region and the second tile region;
forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit along the first direction;
patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches in the first tile region and the second tile region respectively, wherein the second slit trenches along a second direction perpendicular to the first direction;
performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and
filling a second dielectric layer in the second slit trenches to form multiple second slits.
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