US 11,901,306 B2
Semiconductor structure
Chung-Yu Lu, Hsinchu (TW); Yao-Jen Chang, Hsinchu (TW); and Sao-Ling Chiu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 9, 2022, as Appl. No. 18/053,957.
Application 17/226,366 is a division of application No. 16/548,341, filed on Aug. 22, 2019, granted, now 10,978,404, issued on Apr. 13, 2021.
Application 18/053,957 is a continuation of application No. 17/226,366, filed on Apr. 9, 2021, granted, now 11,502,043.
Prior Publication US 2023/0112229 A1, Apr. 13, 2023
Int. Cl. H01L 23/544 (2006.01); H01L 21/308 (2006.01); H01L 21/027 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 21/0274 (2013.01); H01L 21/3083 (2013.01); H01L 2223/54426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a plurality of product regions over a semiconductor substrate;
an alignment region over the semiconductor substrate and surrounded by the product regions;
a plurality of first features formed in a material layer over the semiconductor substrate; and
a plurality of second features formed in the material layer over the semiconductor substrate,
wherein the alignment regions is surrounded by and in physical contact with four of the product regions of a group, and each of the product regions in the group is adjacent to and in physical contact with two other product regions,
wherein each of the first features extends across two adjacent product regions, and each of the second features is disposed within one of the product regions, and wherein the first features are spaced apart from the second features,
wherein the alignment region is free of the first and second features.