US 11,901,299 B2
Interconnect architecture with silicon interposer and EMIB
Md Altaf Hossain, Portland, OR (US); Ankireddy Nalamalpu, Portland, OR (US); Dheeraj Subbareddy, Portland, OR (US); Robert Sankman, Phoenix, AZ (US); Ravindranath V. Mahajan, Chandler, AZ (US); Debendra Mallik, Chandler, AZ (US); Ram S. Viswanath, Phoenix, AZ (US); Sandeep B. Sane, Chandler, AZ (US); Sriram Srinivasan, Chandler, AZ (US); Rajat Agarwal, Portland, OR (US); Aravind Dasu, Milpitas, CA (US); Scott Weber, Piedmont, CA (US); and Ravi Gutala, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 12, 2022, as Appl. No. 18/079,753.
Application 18/079,753 is a continuation of application No. 16/235,879, filed on Dec. 28, 2018, granted, now 11,557,541.
Prior Publication US 2023/0107106 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/5385 (2013.01) [H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/18 (2013.01); H01L 23/481 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2924/381 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a package substrate;
an interposer on the package substrate;
a first die stack and a second die stack on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die stack to the second die stack;
a die on the package substrate; and
an interconnect bridge on the package substrate, wherein the interconnect bridge electrically couples the interposer to the die.