US 11,901,291 B2
Semiconductor devices including lower electrodes including inner protective layer and outer protective layer
Cheoljin Cho, Hwaseong-si (KR); Jungmin Park, Seoul (KR); Hanjin Lim, Seoul (KR); and Jaehyoung Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 20, 2021, as Appl. No. 17/235,369.
Claims priority of application No. 10-2020-0119546 (KR), filed on Sep. 17, 2020.
Prior Publication US 2022/0084943 A1, Mar. 17, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 28/60 (2013.01); H01L 28/75 (2013.01); H01L 28/90 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a landing pad on a substrate;
a lower electrode on the landing pad, the lower electrode including an outer protective layer, a conductive layer between opposing sidewalls of the outer protective layer, and an inner protective layer between opposing sidewalls of the conductive layer;
a first supporter pattern on a side surface of the lower electrode, the first supporter pattern including a supporter hole;
a first metal layer between the conductive layer and the first supporter pattern;
a dielectric layer on a surface of each of the lower electrode and the first supporter pattern; and
an upper electrode on the dielectric layer,
wherein an upper end of the outer protective layer is at a higher level than an upper surface of the conductive layer,
wherein the outer protective layer includes titanium oxide, the conductive layer includes titanium nitride, and the inner protective layer includes titanium silicon nitride,
wherein, in a horizontal cross-sectional view, the outer protective layer has an arc shape that extends between the dielectric layer and the conductive layer, and
wherein the first metal layer overlaps the outer protective layer in a vertical direction.