US 11,901,271 B2
High current packages with reduced solder layer count
Yiqi Tang, Allen, TX (US); Liang Wan, Chengdu (CN); William Todd Harrison, Apex, NC (US); Manu Joseph Prakuzhy, Allen, TX (US); and Rajen Manicon Murugan, Dallas, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Dec. 30, 2022, as Appl. No. 18/148,627.
Application 18/148,627 is a continuation of application No. 16/787,327, filed on Feb. 11, 2020, granted, now 11,545,420.
Claims priority of provisional application 62/804,495, filed on Feb. 12, 2019.
Prior Publication US 2023/0145761 A1, May 11, 2023
Int. Cl. H01L 23/495 (2006.01); H02M 3/158 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49575 (2013.01) [H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 24/32 (2013.01); H02M 3/158 (2013.01); H01L 2224/32245 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a conductive member including a surface;
a power supply connection;
a ground connection;
a first field effect transistor (FET) including a first surface and a second surface opposite the first surface, wherein:
a first solder layer disposed on the first surface of the first FET abuts the surface of the conductive member; and
a first plating layer disposed on the second surface of the first FET abuts the power supply connection; and
a second FET having a third surface and a fourth surface opposite the third surface, wherein:
a second solder layer disposed on the third surface of the second FET abuts the surface of the conductive member; and
a second plating layer disposed on the fourth surface of the second FET abuts the ground connection, wherein the first and second FETs occupy first and second portions of the surface of the conductive member, respectively, the first and second portions not overlapping with each other.