US 11,901,256 B2
Semiconductor device, semiconductor package, and methods of manufacturing the same
Chang-Jung Hsueh, Taipei (TW); Cheng-Nan Lin, Hsinchu (TW); Wan-Yu Chiang, Hsinchu (TW); Wei-Hung Lin, Hsinchu County (TW); Ching-Wen Hsiao, Hsinchu (TW); and Ming-Da Cheng, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/461,999.
Prior Publication US 2023/0068485 A1, Mar. 2, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01)
CPC H01L 23/3185 (2013.01) [H01L 21/78 (2013.01); H01L 23/49822 (2013.01); H01L 23/5226 (2013.01); H01L 24/73 (2013.01); H01L 24/94 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall comprising a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, wherein the first planar sidewall is connected to the second planar sidewall through the curved sidewall;
an interconnect structure, located on the first side of the substrate, wherein a sidewall of the interconnect structure is offset from the second planar sidewall; and
conductive vias, located on the interconnect structure, wherein the interconnect structure is located between the conductive vias and the substrate.