US 11,901,239 B2
Semiconductor device and method for fabricating the same
Chih-Kai Hsu, Tainan (TW); Ssu-I Fu, Kaohsiung (TW); Chun-Ya Chiu, Tainan (TW); Chi-Ting Wu, Tainan (TW); Chin-Hung Chen, Tainan (TW); and Yu-Hsiang Lin, New Taipei (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Feb. 1, 2023, as Appl. No. 18/104,307.
Application 18/104,307 is a continuation of application No. 17/338,696, filed on Jun. 4, 2021, granted, now 11,600,531.
Application 17/338,696 is a continuation of application No. 16/807,108, filed on Mar. 2, 2020, granted, now 11,062,954, issued on Jul. 13, 2021.
Application 16/807,108 is a continuation in part of application No. 15/873,838, filed on Jan. 17, 2018, granted, now 10,607,882, issued on Mar. 31, 2020.
Prior Publication US 2023/0170261 A1, Jun. 1, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/823481 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion;
a first isolation structure on top of the SDB structure;
a first spacer adjacent to and directly contacting the first isolation structure, wherein a top surface of the first spacer is lower than a top surface of the first isolation structure;
a metal gate adjacent to the first isolation structure, wherein a bottom surface of the first spacer is lower than a bottom surface of the metal gate;
a shallow trench isolation (STI) around the fin-shaped structure; and
a second isolation structure on the STI.