US 11,901,237 B2
Semiconductor device having cut gate dielectric
Chang-Yun Chang, Taipei (TW); Bone-Fong Wu, Hsinchu (TW); Ming-Chang Wen, Kaohsiung (TW); and Ya-Hsiu Lin, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/872,103.
Application 16/985,174 is a division of application No. 15/892,593, filed on Feb. 9, 2018, granted, now 10,741,450, issued on Aug. 11, 2020.
Application 17/872,103 is a continuation of application No. 16/985,174, filed on Aug. 4, 2020, granted, now 11,437,278.
Claims priority of provisional application 62/592,843, filed on Nov. 30, 2017.
Prior Publication US 2022/0359302 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/027 (2006.01); H01L 21/265 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02156 (2013.01); H01L 21/31111 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 21/0274 (2013.01); H01L 21/26513 (2013.01); H01L 21/31053 (2013.01); H01L 21/324 (2013.01); H01L 21/76224 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor fin over a substrate;
a gate structure over the semiconductor fin, wherein the gate structure comprises:
a gate dielectric layer over the semiconductor fin; and
a gate metal covering the gate dielectric layer;
gate spacers on opposite sides of the gate structure;
a dielectric feature over the substrate, wherein the dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers; and
an interlayer dielectric (ILD) layer laterally surrounding the gate structure, wherein the dielectric feature comprises:
a first portion in contact with the gate structure; and
a second portion embedded in the ILD layer, wherein a bottom surface of the first portion is lower than a bottom surface of the second portion.