US 11,901,234 B2
Method of processing wafer, and chip measuring apparatus
Takashi Mori, Tokyo (JP); Makoto Kobayashi, Tokyo (JP); Kazunari Tamura, Tokyo (JP); and Okito Umehara, Tokyo (JP)
Assigned to DISCO CORPORATION, Tokyo (JP)
Filed by DISCO CORPORATION, Tokyo (JP)
Filed on Mar. 15, 2023, as Appl. No. 18/184,181.
Application 18/184,181 is a division of application No. 17/024,210, filed on Sep. 17, 2020, granted, now 11,637,039.
Claims priority of application No. 2019-170181 (JP), filed on Sep. 19, 2019.
Prior Publication US 2023/0223303 A1, Jul. 13, 2023
Int. Cl. H01L 21/67 (2006.01); H01L 21/78 (2006.01); H01L 21/66 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 21/67271 (2013.01); H01L 22/12 (2013.01)] 1 Claim
OG exemplary drawing
 
1. A chip measuring apparatus comprising:
a controller for referring to attribute information representing whether a device chip to be inspected is an acceptable device or a defective device;
a strength measuring mechanism for measuring the flexural strength of the device chip by fracturing the device chip if the controller recognizes the attribute information indicating that the device chip includes a defective device; and
a chip observing mechanism for measuring one or more of chipping, reverse side roughness, or side surface roughness of the device chip if the controller recognizes the attribute information indicating that the device chip includes an acceptable device.