US 11,901,180 B2
Method of breaking through etch stop layer
Yu-Shih Wang, Tainan (TW); Hong-Jie Yang, Hsinchu (TW); Chia-Ying Lee, New Taipei (TW); Po-Nan Yeh, Hsinchu (TW); U-Ting Chiu, Hsinchu (TW); Chun-Neng Lin, Hsinchu (TW); Ming-Hsi Yeh, Hsinchu (TW); and Kuo-Bin Huang, Jhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 14, 2022, as Appl. No. 17/670,990.
Application 17/670,990 is a continuation of application No. 16/907,634, filed on Jun. 22, 2020, granted, now 11,276,571.
Claims priority of provisional application 62/953,747, filed on Dec. 26, 2019.
Prior Publication US 2022/0172945 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/027 (2006.01); H01L 21/308 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/0274 (2013.01) [H01L 21/308 (2013.01); H01L 21/823431 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
patterning a resist, the resist overlying a first dielectric layer;
etching the first dielectric layer based on a pattern of the resist to form an opening in the first dielectric layer, the etching stopping on an etch stop layer underlying the first dielectric layer;
while the resist is over the first dielectric layer, extending the opening through the etch stop layer;
after extending the opening through the etch stop layer, etching a second dielectric layer to expose a first metal feature underlying the second dielectric layer, the etched second dielectric layer serving as a mask layer; and
forming a conductive element in the opening in the first dielectric layer, the conductive element electrically coupled to the first metal feature underlying the mask layer.
 
10. A method comprising:
forming a first contact plug extending through a second interlayer dielectric (ILD), an etch stop, and a gate mask dielectric, the first contact plug contacting a source/drain contact, wherein the first contact plug is free from etch damage at an upper surface of the first contact plug; and
forming a second contact plug extending through the second ILD, the etch stop, and the gate mask dielectric, the second contact plug contacting a gate electrode of a gate structure, the gate structure disposed over a semiconductor fin that extends from a substrate, the gate structure comprising: a gate dielectric on the semiconductor fin, the gate electrode on the gate dielectric, and a gate mask over the gate electrode, wherein a first ILD material laterally surrounds the gate structure, the gate mask dielectric extending continuously over an upper surface of the first ILD material, wherein the etch stop is disposed over the gate mask dielectric.
 
17. A method comprising:
forming a mask over a first dielectric layer;
forming a first opening in the mask, the first opening exposing a portion of the first dielectric layer;
etching the first dielectric layer while using the mask as an etch mask to form a second opening in the first dielectric layer, the second opening exposing an etch stop layer;
etching the etch stop layer while using the mask as an etch mask to form a third opening in the etch stop layer; and
forming a first metal feature in the third opening, the first metal feature electrically coupled to a conductive element under the etch stop layer.