US 11,901,176 B2
Semiconductor arrangement and method for making
Yi-Shan Chen, Tainan (TW); and Hao-Heng Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Feb. 20, 2023, as Appl. No. 18/111,792.
Application 18/111,792 is a continuation of application No. 16/689,154, filed on Nov. 20, 2019, granted, now 11,587,782.
Claims priority of provisional application 62/773,335, filed on Nov. 30, 2018.
Prior Publication US 2023/0197439 A1, Jun. 22, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 21/033 (2006.01)
CPC H01L 21/0217 (2013.01) [H01L 21/0332 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor arrangement, comprising:
forming a first dielectric layer;
forming a first semiconductive layer over the first dielectric layer;
forming a photoresist layer over the first semiconductive layer;
patterning the first semiconductive layer using the photoresist layer to form a patterned first semiconductive layer, wherein a first portion of the first dielectric layer is exposed through the patterned first semiconductive layer;
forming a second photoresist layer over the patterned first semiconductive layer, wherein a second portion of the first dielectric layer is exposed through the second photoresist layer, the second portion of the first dielectric layer being a portion of but less than all of the first portion of the first dielectric layer; and
recessing the second portion of the first dielectric layer using the second photoresist layer.