CPC G11C 7/222 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); H03L 7/0818 (2013.01)] | 36 Claims |
1. An apparatus comprising:
at least one memory array; and
an interface coupled to the at least one memory array and configured to be coupled to a memory controller via an interconnect, the interface comprising:
at least one set of first pins configured to receive, from the memory controller, a first differential write clock signal that passes through the interconnect, the first differential write clock signal comprising a first signal having a first phase and a second signal having a second phase that differs from the first phase by approximately 180 degrees; and
at least one set of second pins configured to receive, from the memory controller, a second differential write clock signal that passes through the interconnect, the second differential write clock signal comprising a third signal having a third phase that differs from the first phase and a fourth signal having a fourth phase that differs from the third phase by approximately 180 degrees.
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