US 11,901,039 B2
Multiple differential write clock signals with different phases
Keun Soo Song, Eagle, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,570.
Prior Publication US 2023/0197129 A1, Jun. 22, 2023
Int. Cl. G11C 8/00 (2006.01); G11C 7/22 (2006.01); H03L 7/081 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); H03L 7/0818 (2013.01)] 36 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one memory array; and
an interface coupled to the at least one memory array and configured to be coupled to a memory controller via an interconnect, the interface comprising:
at least one set of first pins configured to receive, from the memory controller, a first differential write clock signal that passes through the interconnect, the first differential write clock signal comprising a first signal having a first phase and a second signal having a second phase that differs from the first phase by approximately 180 degrees; and
at least one set of second pins configured to receive, from the memory controller, a second differential write clock signal that passes through the interconnect, the second differential write clock signal comprising a third signal having a third phase that differs from the first phase and a fourth signal having a fourth phase that differs from the third phase by approximately 180 degrees.