US 11,901,029 B2
Counter-based read in memory device
Umberto Di Vincenzo, Capriate San Gervasio (IT); Riccardo Muzzetto, Arcore (IT); and Ferdinando Bedeschi, Biassono (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 21, 2023, as Appl. No. 18/112,307.
Application 17/590,532 is a division of application No. 16/771,659, granted, now 11,244,739, issued on Feb. 8, 2022, previously published as PCT/IB2019/001260, filed on Dec. 23, 2019.
Application 18/112,307 is a continuation of application No. 17/590,532, filed on Feb. 1, 2022, granted, now 11,594,297.
Prior Publication US 2023/0282301 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 7/14 (2006.01); G11C 29/20 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/14 (2013.01); G11C 29/12005 (2013.01); G11C 29/20 (2013.01); G11C 29/44 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
accessing a memory cell of a memory device;
generating a voltage for the memory cell based on the accessing;
generating a reference voltage; and
modifying the reference voltage until a count of one or more other memory cells of the memory device determined to be in a logic state meets a criterium.