US 11,901,024 B2
Method and device for testing memory chip
Dong Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 28, 2022, as Appl. No. 17/851,656.
Application 17/851,656 is a continuation of application No. PCT/CN2022/086403, filed on Apr. 12, 2022.
Claims priority of application No. 202210153533.8 (CN), filed on Feb. 18, 2022.
Prior Publication US 2023/0268019 A1, Aug. 24, 2023
Int. Cl. G11C 29/12 (2006.01)
CPC G11C 29/12005 (2013.01) [G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for testing a memory chip, comprising:
writing test data into memory cells of a memory chip to-be-tested;
reading stored data from the memory cells; and
generating a test result of the memory chip to-be-tested according to the test data and the stored data,
wherein a word line turn-on voltage tested in the memory chip to-be-tested is greater than a standard bit line and word line turn-on voltage of the memory chip to-be-tested, and/or a sense amplification time tested in the memory chip to-be-tested is greater than a standard sense amplification time of the memory chip to-be-tested.