CPC G11C 16/3459 (2013.01) [G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a memory cell string that includes memory cells (MCs) that are connected in series;
word line layers coupled respectively with the MCs, the word line layers including a selected word line layer coupled to one of the MCs that is selected for a verify or read operation, and an unselected word line layer coupled to one of the MCs that is not selected for the verify or read operation; and
processing circuitry configured to:
apply, in a pre-pulse stage, a first verify/read bias voltage on the selected word line layer;
apply, in the pre-pulse stage, a first bias voltage on the unselected word line layer;
apply, in a verify/read stage, a second verify/read voltage on the selected word line layer; and
apply, in the verify/read stage, a second bias voltage on the unselected word line layer, wherein the second bias voltage is smaller than the first bias voltage.
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