US 11,901,023 B2
Architecture and method for NAND memory operation
Changhyun Lee, Wuhan (CN); Xiangnan Zhao, Wuhan (CN); and Haibo Li, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Sep. 15, 2022, as Appl. No. 17/945,783.
Application 17/945,783 is a continuation of application No. 17/191,768, filed on Mar. 4, 2021, granted, now 11,468,957.
Application 17/191,768 is a continuation of application No. PCT/CN2020/136482, filed on Dec. 15, 2020.
Prior Publication US 2023/0020789 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell string that includes memory cells (MCs) that are connected in series;
word line layers coupled respectively with the MCs, the word line layers including a selected word line layer coupled to one of the MCs that is selected for a verify or read operation, and an unselected word line layer coupled to one of the MCs that is not selected for the verify or read operation; and
processing circuitry configured to:
apply, in a pre-pulse stage, a first verify/read bias voltage on the selected word line layer;
apply, in the pre-pulse stage, a first bias voltage on the unselected word line layer;
apply, in a verify/read stage, a second verify/read voltage on the selected word line layer; and
apply, in the verify/read stage, a second bias voltage on the unselected word line layer, wherein the second bias voltage is smaller than the first bias voltage.