US 11,901,019 B2
Use of data latches for compression of soft bit data in non-volatile memories
Hua-Ling Cynthia Hsu, Milpitas, CA (US); Masaaki Higashitani, Cupertino, CA (US); YenLung Li, San Jose, CA (US); and Chen Chen, Mountain View, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Feb. 8, 2022, as Appl. No. 17/666,657.
Application 17/666,657 is a continuation in part of application No. 17/557,236, filed on Dec. 21, 2021.
Claims priority of provisional application 63/244,951, filed on Sep. 16, 2021.
Prior Publication US 2023/0081623 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/26 (2006.01); G11C 16/24 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); H03M 13/1111 (2013.01); H03M 13/611 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a control circuit configured to connect to a plurality of bit lines each connected to a corresponding plurality of memory cells, the control circuit comprising:
a plurality of sense amplifiers each configured to read data from the memory cells connected to a corresponding one or more bit lines;
a plurality of sets of internal data latches, each set of internal data latches configured to store data associated with a corresponding one of the sense amplifiers;
a cache buffer comprising a plurality of sets of transfer data latches each corresponding to one of the sets of internal data latches; and
an input-output interface configured to provide data to an external data bus, the control circuit configured to:
perform a read operation by each of the sense amplifiers on a plurality of memory cells;
store results of the read operation by each of the sense amplifiers in the corresponding set of internal data latches;
compress the results of the read operation by each of the sense amplifiers within the corresponding set of internal data latches;
transfer the compressed results of the read operation from each of the set of internal data latches to a corresponding set of transfer data latches;
compact the compressed results of the read operation from the sets of transfer data latches into a smaller number of the sets of transfer latches; and
transfer the compacted compressed results of the read operation over the input-output interface to the external data bus.