US 11,901,017 B2
Semiconductor memory device and method of operating the same
Hee Youl Lee, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Oct. 4, 2021, as Appl. No. 17/493,438.
Claims priority of application No. 10-2021-0063708 (KR), filed on May 17, 2021.
Prior Publication US 2022/0366989 A1, Nov. 17, 2022
Int. Cl. G11C 11/34 (2006.01); G11C 16/26 (2006.01); G11C 16/24 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01); G11C 11/56 (2013.01); G11C 16/0483 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of operating a semiconductor memory device configured to perform a read operation on selected memory cells, the method comprising:
determining a read voltage to be used in the read operation among first to 2N−1-th read voltages, wherein N is a natural number of 2 or more;
applying a determined read voltage to a selected word line connected to the selected memory cells; and
applying a first read pass voltage or a second read pass voltage greater than the first read pass voltage to adjacent word lines that are adjacent to the selected word line among unselected word lines based on whether the determined read voltage is the first read voltage among the first to 2N−1-th read voltages.