US 11,901,014 B2
Partial block handling in a non-volatile memory device
Zhongguang Xu, San Jose, CA (US); Nicola Ciocchini, Boise, ID (US); Zhenlei Shen, Milpitas, CA (US); Charles See Yeung Kwong, Redwood City, CA (US); Murong Lang, San Jose, CA (US); Ugo Russo, Boise, ID (US); and Niccolo' Righetti, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 9, 2022, as Appl. No. 17/739,741.
Prior Publication US 2023/0360704 A1, Nov. 9, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3481 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
initiating a partial block handling protocol for a closed block of the memory device, the block comprising a plurality of wordlines;
sending a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed; and
sending a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.