US 11,901,010 B2
Enhanced gradient seeding scheme during a program operation in a memory sub-system
Vinh Q. Diep, Hayward, CA (US); Ching-Huang Lu, Fremont, CA (US); and Yingda Dong, Los Altos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 16, 2020, as Appl. No. 17/247,576.
Prior Publication US 2022/0189555 A1, Jun. 16, 2022
Int. Cl. G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/30 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a program operation on the memory array, the program operation comprising a seeding phase;
causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation;
causing a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation, at least one word line adjacent to the selected word line on a drain-side of the selected word line, and at least one word line adjacent to the selected word line on a source-side of the selected word line; and
causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.