US 11,900,989 B2
Memory array with multiplexed digit lines
Ferdinando Bedeschi, Biassono (IT); and Stefan Frederik Schippers, Peschiera del Garda (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 8, 2021, as Appl. No. 17/370,488.
Application 17/370,488 is a division of application No. 16/379,222, filed on Apr. 9, 2019, granted, now 11,062,763.
Prior Publication US 2021/0407581 A1, Dec. 30, 2021
Int. Cl. G11C 11/40 (2006.01); G11C 11/4096 (2006.01); G11C 11/4091 (2006.01); G11C 11/408 (2006.01); H10B 12/00 (2023.01); G11C 11/56 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); H10B 12/30 (2023.02); H10B 12/50 (2023.02); G11C 11/4087 (2013.01); G11C 11/565 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate; and
a memory cell comprising a storage component, a first vertical transistor, and a second vertical transistor,
the first vertical transistor comprising a first gate coupled with a word line and a first doped region extending in a first direction away from a surface of the substrate; and
the second vertical transistor comprising a second gate coupled with a select line and a second doped region extending in the first direction away from the surface of the substrate, the first vertical transistor is a first distance away from the substrate and the second vertical transistor is above the first vertical transistor a second distance away from the substrate different than the first distance, and the word line is a third distance away from the surface of the substrate and the select line is above the word line a fourth distance away from the surface of the substrate different than the third distance.