US 11,900,984 B2
Data destruction
Torsten Partsch, San Jose, CA (US); John Eric Linstadt, Palo Alto, CA (US); and Helena Handschuh, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jan. 31, 2023, as Appl. No. 18/104,069.
Application 18/104,069 is a continuation of application No. 17/325,977, filed on May 20, 2021, granted, now 11,600,316.
Claims priority of provisional application 63/031,150, filed on May 28, 2020.
Prior Publication US 2023/0260564 A1, Aug. 17, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 11/406 (2006.01); G11C 11/4091 (2006.01); G11C 11/4076 (2006.01); G11C 11/4094 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40626 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module, comprising:
a first integrated circuit to detect a secure shutdown event and to provide an indicator of the secure shutdown event;
a plurality of memory components comprising blocks of memory cells, a first memory component of the plurality of memory components comprising a first sense amplifier circuit and a first block of memory cells, the first block of memory cells coupled to a plurality of wordlines and a plurality of bitlines of a memory array, the plurality of bitlines including a first bitline coupled to a plurality of memory cells respectively coupled to the plurality of wordlines and the first bitline;
the first memory component to, based on the indicator of the secure shutdown event, erase the block of memory cells by causing activations of the plurality of wordlines of the first block of memory cells to occur concurrently, concurrent activation of the plurality of wordlines to cause a sharing, with the first bitline, of a plurality of charges held by the plurality of memory cells; and
the first sense amplifier circuit is to amplify a voltage difference resulting from the sharing of the plurality of charges held by the plurality of memory cells to a writeback voltage that is written to each of the plurality of memory cells.