	US 11,900,980 B2
	Techniques to mitigate asymmetric long delay stress
Angelo Visconti, Appiano Gentile (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,614.
Application 17/690,614 is a continuation of application No. 17/103,552, filed on Nov. 24, 2020, granted, now 11,295,797.
Prior Publication US 2022/0199138 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/12 (2006.01); G11C 11/22 (2006.01)

CPC G11C 11/2259 (2013.01) [G11C 11/221 (2013.01); G11C 11/2275 (2013.01)]

17 Claims

1. A method, comprising:

activating a memory cell during a first phase of an access operation cycle;

writing, at a first time of the first phase of the access operation cycle, a first state to the memory cell;

writing the first state or a second state to the memory cell at a second time during the first phase of the access operation cycle different from the first time;

maintaining the first state or the second state at the memory cell during a second phase of the access operation cycle after the first phase of the access operation cycle; and

precharging the memory cell during a third phase of the access operation cycle after the second phase of the access operation cycle.