US 11,900,894 B2
Display panel
Jae-Hoon Lee, Seoul (KR); Seung-Hwan Moon, Asan-si (KR); Yong-Soon Lee, Cheonan-si (KR); Young-Su Kim, Daegu (KR); Chang-Ho Lee, Seoul (KR); Whee-Won Lee, Seoul (KR); Jun-Yong Song, Busan (KR); and Yu-Han Bae, Seoul (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Jan. 12, 2023, as Appl. No. 18/096,063.
Application 18/096,063 is a continuation of application No. 17/406,632, filed on Aug. 19, 2021, granted, now 11,580,926.
Application 17/406,632 is a continuation of application No. 16/860,164, filed on Apr. 28, 2020, granted, now 11,100,881, issued on Aug. 24, 2021.
Application 16/860,164 is a continuation of application No. 16/553,642, filed on Aug. 28, 2019, granted, now 10,770,020, issued on Sep. 8, 2020.
Application 16/553,642 is a continuation of application No. 15/613,698, filed on Jun. 5, 2017, granted, now 10,403,221, issued on Sep. 3, 2019.
Application 15/613,698 is a continuation of application No. 12/949,931, filed on Nov. 19, 2010, granted, now 9,672,782, issued on Jun. 6, 2017.
Claims priority of application No. 10-2009-0115171 (KR), filed on Nov. 26, 2009.
Prior Publication US 2023/0146693 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 19/00 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/3677 (2013.01) [G11C 19/28 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a display area including a gate line;
a gate driver electrically connected to the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a first transistor including a control electrode electrically connected to a first node, a first electrode electrically connected to a clock signal line, and a second electrode electrically connected to the gate line;
a third transistor including a control electrode electrically connected to a second node which is different from the first node, a first electrode electrically connected to a first voff signal line to which a first voff signal is input, and a second electrode electrically connected to the second electrode of the first transistor;
a fifth transistor including a control electrode, a first electrode electrically connected to a second voff signal line, and a second electrode electrically connected to the second node;
an eleventh transistor including a control electrode electrically connected to the second node, a first electrode electrically connected to the second voff signal line, and a second electrode electrically connected to a carry signal out terminal; and
a fifteenth transistor including a control electrode electrically connected to the first node, a first electrode, and a second electrode electrically connected to the carry signal out terminal.