US 11,900,883 B2
Shift register unit, method for driving shift register unit, gate driving circuit, and display device
Guangliang Shang, Beijing (CN); Can Zheng, Beijing (CN); Jiangnan Lu, Beijing (CN); Yuhan Qian, Beijing (CN); Li Wang, Beijing (CN); Libin Liu, Beijing (CN); Shiming Shi, Beijing (CN); and Dawei Wang, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/630,634
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Mar. 19, 2021, PCT No. PCT/CN2021/081786
§ 371(c)(1), (2) Date Jan. 27, 2022,
PCT Pub. No. WO2022/193281, PCT Pub. Date Sep. 22, 2022.
Prior Publication US 2023/0360608 A1, Nov. 9, 2023
Int. Cl. G11C 19/28 (2006.01); G09G 3/3266 (2016.01)
CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); G09G 2310/0286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register unit, comprising: a first shift register circuit module and a second shift register circuit module,
wherein the first shift register circuit module is configured to output a first output signal at a first output terminal according to an input signal received by an input terminal and is configured to provide a turn-on control signal to the second shift register circuit module; and
the second shift register circuit module comprises an output circuit, a noise reduction circuit, a first noise reduction control circuit, and a second noise reduction control circuit, the output circuit is configured to output a second output signal at a second output terminal in response to the turn-on control signal,
the noise reduction circuit is configured to perform noise reduction on the second output terminal under control of a level of a first noise reduction control node,
the first noise reduction control circuit is configured to control the level of the first noise reduction control node to turn off the noise reduction circuit in response to the first output signal, and
the second noise reduction control circuit is configured to adjust the level of the first noise reduction control node to turn on the noise reduction circuit under control of a first clock signal and a second clock signal,
wherein the second noise reduction control circuit comprises a first control circuit, a first coupling circuit, a second coupling circuit, a transmission circuit, and a storage circuit, the first control circuit is configured to transmit a first voltage to a second noise reduction control node under control of the first clock signal,
the first coupling circuit is configured to store a level of the second noise reduction control node and adjust the level of the second noise reduction control node under control of the second clock signal,
the second coupling circuit is configured to store the level of the second noise reduction control node and reduce an adjustment magnitude of the first coupling circuit in case of adjusting the level of the second noise reduction control node,
the transmission circuit is configured to connect the first noise reduction control node and the second noise reduction control node to balance the level of the first noise reduction control node and the level of the second noise reduction control node, and
the storage circuit is configured to store the level of the first noise reduction control node.