US 11,900,842 B1
Irregular devices
Jonathan Seamus Blackley, South Pasadena, CA (US); Watson Brent Boyett, Los Angeles, CA (US); Sylvain Marcel Colin, Ventura, CA (US); Robin James Green, Duvall, WA (US); Stephen John Hart, San Juan Capistrano, CA (US); Margaret H. Hsu, Pasadena, CA (US); DeaGyu Kim, Pasadena, CA (US); Mark Anthony Loya, Temple City, CA (US); Benjamin Francis Neil, South Pasadena, CA (US); Kamran Qaderi, San Gabriel, CA (US); Tina Qin, Rosemead, CA (US); Jesus Manuel Caridad Ramirez, Altadena, CA (US); Jayakrishna Sashidharan, San Gabriel, CA (US); Asher Zelig Sefami, Altadena, CA (US); Sameer Sudhir Walavalkar, Glendale, CA (US); and Joshua D. Wiensch, Altadena, CA (US)
Assigned to Pacific Light & Hologram, Inc., San Gabriel, CA (US)
Filed by Pacific Light & Hologram, Inc., San Gabriel, CA (US)
Filed on Sep. 15, 2023, as Appl. No. 18/468,571.
Claims priority of provisional application 63/501,928, filed on May 12, 2023.
Int. Cl. G09G 3/00 (2006.01); G02F 1/1343 (2006.01); G09G 3/34 (2006.01); G09G 3/36 (2006.01)
CPC G09G 3/003 (2013.01) [G02F 1/13439 (2013.01); G02F 1/134309 (2013.01); G09G 3/3413 (2013.01); G09G 3/36 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A device comprising:
a backplane comprising a plurality of circuits; and
a plurality of elements on the backplane, the plurality of elements forming an irregular pattern,
wherein the plurality of elements are coupled to the plurality of circuits by conductive vias that are regularly spaced,
wherein the device comprises:
a liquid crystal layer;
a transparent conductive layer on a top side of the liquid crystal layer as a common electrode; and
a plurality of metallic electrodes on a bottom side of the liquid crystal layer,
wherein each of the plurality of metallic electrodes is conductively isolated from each other and individually controllable by the backplane, and wherein each of the plurality of metallic electrodes is one-to-one conductively coupled to a respective circuit of the plurality of circuits in the backplane via a corresponding conductive via of the conductive vias, and
wherein the plurality of metallic electrodes comprise multiple pairs of layers of metallic electrodes and conductive vias that are sequentially stacked between the liquid crystal layer and the plurality of circuits along a first direction, wherein first conductive vias of a first pair of the multiple pairs are positioned between the plurality of circuits and first metallic electrodes of the first pair and regularly spaced along a second direction perpendicular to the first direction, and second conductive vias of a second pair of the multiple pairs are positioned between the first metallic electrodes of the first pair and second metallic electrodes of the second pair and regularly spaced along the second direction, and wherein adjacent first conductive via and second conductive via are offset from each other along the second direction.