US 11,900,539 B2
Tile sequencing mechanism
Subramaniam Maiyuran, Gold River, CA (US); Saurabh Sharma, El Dorado Hills, CA (US); Jorge F. Garcia Pabon, Folsom, CA (US); Raghavendra Kamath Miyar, Bangalore (IN); Sudheendra Srivathsa, Bangalore (IN); Justin Decell, San Francisco, CA (US); and Aditya Navale, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 1, 2022, as Appl. No. 17/590,521.
Application 17/590,521 is a continuation of application No. 16/914,783, filed on Jun. 29, 2020, granted, now 11,250,627.
Prior Publication US 2022/0262070 A1, Aug. 18, 2022
Int. Cl. G06T 15/00 (2011.01); G06T 17/20 (2006.01); G06T 1/20 (2006.01)
CPC G06T 17/20 (2013.01) [G06T 1/20 (2013.01); G06T 15/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a graphics processor including graphics processing resources configured for tile-based immediate-mode rendering, the graphics processor including:
a cache memory to store object data and associated control data for objects to be rendered by the graphics processor; and
sequencer circuitry to:
generate a plurality of batches of the objects to be rendered, each of the plurality of batches sized according to a size of the cache memory,
determine tiles intersected by objects in each of the plurality of batches,
maintain lit transaction information for the plurality of batches based on the intersected tiles, and
perform a play sequencing of each of the objects based on the lit transaction information,
wherein to perform the play sequencing includes to:
select, based on the lit transaction information, a cache aware tile-walk pattern; and
walk lit tiles according to the tile-walk pattern, wherein to walk a lit tile includes to process primitive commands for objects in the plurality of batches of objects that are associated with the lit tile.