US 11,900,523 B2
Early termination in bottom-up acceleration data structure refit
Kai Xiao, San Jose, CA (US); Michael Apodaca, El Dorado Hills, CA (US); Carson Brownlee, Santa Clara, CA (US); Thomas Raoux, Sunnyvale, CA (US); Joshua Barczak, Forest Hill, MD (US); and Gabor Liktor, San Francisco, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 19, 2021, as Appl. No. 17/505,387.
Application 17/505,387 is a continuation of application No. 16/915,599, filed on Jun. 29, 2020, granted, now 11,158,111.
Application 16/915,599 is a continuation of application No. 16/235,583, filed on Dec. 28, 2018, granted, now 10,740,953, issued on Aug. 11, 2020.
Prior Publication US 2022/0108518 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/06 (2011.01); G06T 1/20 (2006.01)
CPC G06T 15/06 (2013.01) [G06T 1/20 (2013.01); G06T 2200/04 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes;
traversal hardware logic to traverse one or more rays through the hierarchical acceleration data structure;
intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; and
a node refit unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure to adjust spatial dimensions of one or more of the nodes,
wherein the node refit unit is to receive refit data associated with refitting one or more child nodes of a current node and to skip refitting the current node responsive to that the refit data indicates that space occupancy of the one or more child nodes has shrunk but the one or more child nodes are still bounded by the current node.