US 11,900,502 B2
Compiler assisted register file write reduction
Chandra S. Gurram, Folsom, CA (US); Gang Y. Chen, Milpitas, CA (US); Subramaniam Maiyuran, Gold River, CA (US); Supratim Pal, Folsom, CA (US); Ashutosh Garg, Folsom, CA (US); Jorge E. Parra, El Dorado Hills, CA (US); Darin M. Starkey, Roseville, CA (US); Guei-Yuan Lueh, San Jose, CA (US); and Wei-Yu Chen, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 2, 2022, as Appl. No. 17/734,983.
Application 17/734,983 is a division of application No. 16/726,659, filed on Dec. 24, 2019, granted, now 11,321,799.
Prior Publication US 2022/0261949 A1, Aug. 18, 2022
Int. Cl. G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium comprising instructions stored thereon, that if executed by a processor, cause the processor to:
execute a compiler that is to:
receive a program for execution by a graphics processing unit (GPU);
identify a group of two or more instructions in the program that provide a partial update to an output buffer;
include a first instruction in the group of two or more instructions to trigger a transfer that causes writing of an output from execution of the group of two or more instructions to an intermediate buffer;
include a second instruction in the group of two or more instructions that causes copying of content of the intermediate buffer to the output buffer;
format the group of two or more instructions with the first and second instructions for execution by the GPU; and
store a machine executable format of the group of two or more instructions with the first and second instructions.