US 11,900,253 B2
Tiling format for convolutional neural networks
Song Zhang, Shanghai (CN); Jiantan Liu, Shanghai (CN); Hua Zhang, Shanghai (CN); and Min Yu, Shanghai (CN)
Assigned to Advanced Mic ro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Oct. 28, 2022, as Appl. No. 18/050,939.
Application 18/050,939 is a continuation of application No. 17/006,533, filed on Aug. 28, 2020, granted, now 11,494,592, issued on Nov. 8, 2022.
Application 17/006,533 is a continuation of application No. 16/234,956, filed on Dec. 28, 2018, granted, now 10,762,392, issued on Sep. 1, 2020.
Claims priority of application No. 201811563959.0 (CN), filed on Dec. 20, 2018.
Prior Publication US 2023/0186084 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/08 (2023.01); G06N 3/04 (2023.01); G06F 18/21 (2023.01); G06V 10/82 (2022.01); G06V 10/44 (2022.01); G06V 10/50 (2022.01); G06V 10/94 (2022.01)
CPC G06N 3/08 (2013.01) [G06F 18/217 (2023.01); G06N 3/04 (2013.01); G06V 10/449 (2022.01); G06V 10/454 (2022.01); G06V 10/50 (2022.01); G06V 10/82 (2022.01); G06V 10/955 (2022.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor comprising circuitry, wherein in response to a request to perform a convolutional filter operation, the processor is configured to:
read convolutional data stored in a linear format from sequential locations in a memory device; and
convert the convolutional data from the linear format to a tiling format by writing the read convolutional data to memory locations according to a stride greater than one.