| CPC G06F 9/4881 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30079 (2013.01); G06F 9/505 (2013.01); G06F 9/5077 (2013.01)] | 21 Claims |
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1. An electronic processing system, comprising:
a general processor;
a graphics processor;
memory communicatively coupled to the general processor and the graphics processor; and
logic communicatively coupled to the general processor and the graphics processor to:
manage one or more virtual graphic processor units,
map schedule information into a graphics memory space, wherein the schedule information includes schedule account information,
co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions,
co-schedule the one or more virtual graphic processor units based on the graphics processor instructions when a graphics processor schedule stub inserted at an end of a virtual graphics processor workload is reached, and
update the schedule account information in the graphics memory space based on one or more of graphics memory space access instructions and graphics processor pipeline instructions, wherein the schedule account information is associated with scheduling policies implemented by graphics processor commands.
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