US 11,900,122 B2
Methods and systems for inter-pipeline data hazard avoidance
Luca Iuliano, Chesham (GB); Simon Nield, Wendover (GB); Yoong-Chert Foo, London (GB); and Ollie Mower, Harrow (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Jul. 10, 2023, as Appl. No. 18/220,048.
Application 18/220,048 is a continuation of application No. 17/523,633, filed on Nov. 10, 2021, granted, now 11,698,790.
Application 17/523,633 is a continuation of application No. 17/070,316, filed on Oct. 14, 2020, granted, now 11,200,064, issued on Dec. 14, 2021.
Application 17/070,316 is a continuation of application No. 16/009,358, filed on Jun. 15, 2018, granted, now 10,817,301, issued on Oct. 27, 2020.
Claims priority of application No. 1709598 (GB), filed on Jun. 16, 2017; and application No. 1720408 (GB), filed on Dec. 7, 2017.
Prior Publication US 2023/0350689 A1, Nov. 2, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3861 (2013.01) [G06F 9/3016 (2013.01); G06F 9/3834 (2013.01); G06F 9/3838 (2013.01); G06F 9/3867 (2013.01); G06F 9/3889 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of processing instructions in a parallel processing unit comprising a plurality of instruction pipelines, the method comprising:
tracking data hazards using a plurality of counters, the plurality of counters comprising a first set of counters associated with high latency data hazards and a second set of counters associated with low latency data hazards; and
at an instruction decoder:
receiving an instruction for execution that indicates (i) whether the instruction is a primary instruction from which at least one other instruction is dependent and if so, a counter of the plurality of counters the primary instruction is associated with and (ii) whether the instruction is a secondary instruction and if so, the counters of the plurality of counters associated with the primary instructions from which the instruction depends,
determining whether the instruction is a secondary instruction,
if it is determined that the instruction is a secondary instruction, determining from the counters associated with the primary instructions from which the instruction depends, whether the instruction relates to at least one high latency data hazard,
if it is determined that the instruction relates to at least one high latency data hazard, determining from the plurality of counters whether each high latency data hazard related to the instruction has been resolved,
if it is determined that at least one high latency data hazard related to the instruction has not been resolved, causing the instruction to be de-scheduled until each high latency data hazard related to the instruction has been resolved, and
if it is determined that the instruction does not relate to at least one high latency data hazard or that all of the high latency data hazards related to the instruction have been resolved, forwarding the instruction to a queue preceding an appropriate instruction pipeline where the instruction stalls until all low latency data hazards related to the instruction have been resolved.